ADSP-21469 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

ADSP-21469

SHARC Processor

Analog Devices 

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S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 52. S/PDIF Receiver Internal Digital PLL Mode Timing

Parameter

Switching Characteristics

tDFSI

LRCLK Delay After Serial Clock

tHOFSI

LRCLK Hold After Serial Clock

tDDTI

Transmit Data Delay After Serial Clock

tHDTI

tSCLKIW1

Transmit Data Hold After Serial Clock

Transmit Serial Clock Width

1 Serial clock frequency is 64 × Frame Sync, where FS = the frequency of LRCLK.

ADSP-21467/ADSP-21469

Min

Max

Unit

5

ns

–2

ns

5

ns

–2

ns

8 × tPCLK – 2

ns

DRIVE EDGE

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

tDFSI

tHOFSI

tDDTI

tHDTI

tSCLKIW

SAMPLE EDGE

Figure 39. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. B | Page 55 of 76 | March 2013

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