ADSP-21469 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469' PDF : 56 Pages View PDF
Table 49. S/PDIF Transmitter Left-Justified Mode
Parameter
Timing Requirement
tLJD
LRCLK to MSB Delay in Left-Justified Mode
ADSP-21467/ADSP-21469
Nominal
0
Unit
SCLK
DAI_P20–1
FS
DAI_P20–1
SCLK
DAI_P20–1
SDATA
LEFT/RIGHT CHANNEL
tLJD
MSB MSB–1 MSB–2
LSB+2 LSB+1 LSB
Figure 37. Left-Justified Mode
S/PDIF Transmitter Input Data Timing
The timing requirements for the S/PDIF transmitter are given
in Table 50. Input signals are routed to the DAI_P20–1 pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P20–1 pins.
Table 50. S/PDIF Transmitter Input Data Timing
Parameter
Min
Max
Unit
Timing Requirements
tSISFS1
Frame Sync Setup Before Serial Clock Rising Edge
3
ns
tSIHFS1
Frame Sync Hold After Serial Clock Rising Edge
3
ns
tSISD1
Data Setup Before Serial Clock Rising Edge
3
ns
tSIHD1
Data Hold After Serial Clock Rising Edge
3
ns
tSITXCLKW
Transmit Clock Width
9
ns
tSITXCLK
Transmit Clock Period
20
ns
tSISCLKW
Clock Width
36
ns
tSISCLK
Clock Period
80
ns
1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. The PCG’s input
can be either CLKIN or any of the DAI pins.
Rev. B | Page 53 of 76 | March 2013
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