ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
Preliminary Technical Data
ADSP-21469/ADSP-21469W
Reset
Table 15. Reset
Parameter
Min
Max
Unit
Timing Requirements
tWRST1
RESET Pulse Width Low
TBD
TBD
ns
tSRST
RESET Setup Before CLKIN Low
TBD
TBD
ns
1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μσ while RESET is low, assuming stable
VDD and CLKIN (not including start-up time of external clock oscillator).
CLKIN
RESET
tWRST
tSRST
Figure 7. Reset
Running Reset
The following timing specification applies to CLKOUT/
RESETOUT/RUNRSTIN pin when it is configured as
RUNRSTIN.
Table 16. Running Reset
Parameter
Min
Timing Requirements
tWRUNRST
tSRUNRST
Running RESET Pulse Width Low
TBD
Running RESET Setup Before CLKIN High
TBD
Max
Unit
TBD
ns
TBD
ns
CLKIN
RUNRSTIN
tWRUNRST
tSRUNRST
Figure 8. Running Reset
Rev. PrB | Page 23 of 56 | November 2008
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