ADSP-21469/ADSP-21469W
Preliminary Technical Data
DDR2 SDRAM Read Cycle Timing
Table 24. DDR2 SDRAM Read Cycle Timing, VDD-DDR2 nominal 1.8V
Parameter
Timing Requirements
TBD
Symbol
TBD
Minimum
TBD
TBD
Figure 16. DDR2 SDRAM Controller Input AC Timing
Maximum Unit
TBD
TBD
Rev. PrB | Page 28 of 56 | November 2008