ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
ADSP-21469/ADSP-21469W
Preliminary Technical Data
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD,
AMI_WR, and strobe timing parameters only apply to asyn-
chronous access mode.
Table 26. Memory Read—Bus Master
Parameter
Min
Max
Unit
Timing Requirements
tDAD
Address, Selects Delay to Data Valid1, 2
TBD
TBD
ns
tDRLD
AMI_RD Low to Data Valid1
TBD
TBD
ns
tSDS
Data Setup to AMI_RD High
TBD
TBD
ns
tHDRH
Data Hold from AMI_RD High3, 4
TBD
TBD
ns
tDAAK
AMI_ACK Delay from Address, Selects2, 5
TBD
TBD
ns
tDSAK
AMI_ACK Delay from AMI_RD Low4
TBD
TBD
ns
Switching Characteristics
TBD
TBD
tDRHA
Address Selects Hold After AMI_RD High
TBD
TBD
ns
tDARL
Address Selects to AMI_RD Low2
TBD
TBD
ns
tRW
AMI_RD Pulse Width
TBD
TBD
ns
tRWR
AMI_RD High to AMI_WR, AMI_RD, Low
TBD
TBD
ns
W = (number of wait states specified in AMICTLx register) × tDDR2_CLK.
HI = RHC + IC (RHC = (number of Read Hold Cycles specified in AMICTLx register) x tDDR2_CLK
IC = (number of idle cycles specified in AMICTLx register) x tDDR2_CLK).
H = (number of hold cycles specified in AMICTLx register) x tDDR2_CLK.
1 Data delay/setup: System must meet tDAD, tDRLD, or tSDS.
2 The falling edge of AMI_MSx, is referenced.
3 Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asynchronous access mode.
4 Data hold: User must meet tHDRH in asynchronous access mode. See Test Conditions on Page 50 for the calculation of hold times given capacitive and dc loads.
5 AMI_ACK delay/setup: User must meet tDAAK, or tDSAK, for deassertion of AMI_ACK (low). For asynchronous assertion of AMI_ACK (high) user must meet tDAAK or tDSAK.
AMI_ADDR
MSx
AMI_RD
AMI_DATA
AMI_ACK
tDARL
tRW
tDAAK
tDAD
tDRLD
tDSAK
tSDS
tDRHA
tHDRH
tRWR
AMI_WR
Figure 18. Memory Read—Bus Master
Rev. PrB | Page 30 of 56 | November 2008
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