ADSP-21469KBZ-ENG2 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-21469KBZ-ENG2' PDF : 56 Pages View PDF
ADSP-21469/ADSP-21469W
Preliminary Technical Data
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the precision clock generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG’s
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P01 – DAI_P20).
Table 22. Precision Clock Generator (Direct Pin Routing)
Parameter
Min
Max
Unit
Timing Requirements
tPCGIW
tSTRIG
Input Clock Period
TBD
PCG Trigger Setup Before Falling Edge of PCG Input TBD
Clock
TBD
ns
TBD
ns
tHTRIG
PCG Trigger Hold After Falling Edge of PCG Input TBD
Clock
TBD
ns
Switching Characteristics
tDPCGIO
PCG Output Clock and Frame Sync Active Edge Delay
After PCG Input Clock
TBD
TBD
ns
tDTRIGCLK PCG Output Clock Delay After PCG Trigger
TBD
TBD
ns
tDTRIGFS
PCG Frame Sync Delay After PCG Trigger
TBD
tPCGOW1
Output Clock Period
TBD
TBD
ns
TBD
ns
D = FSxDIV, PH = FSxPHASE. For more information, see the ADSP-2146x SHARC Processor Hardware Reference, “Precision Clock Generators”
chapter.
1 Normal mode of operation.
DAI_Pn
DPI_Pn
PCG_TRIGx_I
tSTRIG
DAI_Pm
DPI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
DPI_Py
PCG_CLKx_O
tHTRIG
tDPCG IO
tDTRIGCLK
tPCGIW
tDPCGIO
DAI_Pz
DPI_Pz
PCG_FSx_O
tD TRIGF S
Figure 14. Precision Clock Generator (Direct Pin Routing)
tPCGOW
Rev. PrB | Page 26 of 56 | November 2008
Share Link: 
