ADSP-BF522BBCZ-3A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF522BBCZ-3A' PDF : 88 Pages View PDF
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Timer Clock Timing
Table 54 and Figure 32 describe timer clock timing.
Table 54. Timer Clock Timing
Parameter
Switching Characteristic
tTODP
Timer Output Update Delay After PPI_CLK High
VDDEXT
1.8V Nominal
Min
Max
12.0
VDDEXT
2.5 V or 3.3V Nominal
Min
Max
Unit
12.0
ns
PPI_CLK
TMRx OUTPUT
tTODP
Figure 32. Timer Clock Timing
Up/Down Counter/Rotary Encoder Timing
Table 55. Up/Down Counter/Rotary Encoder Timing
VDDEXT
1.8V Nominal
Parameter
Min
Max
Timing Requirements
tWCOUNT
tCIS
tCIH
Up/Down Counter/Rotary Encoder Input Pulse Width tSCLK + 1
Counter Input Setup Time Before CLKOUT High1
9.0
Counter Input Hold Time After CLKOUT High1
0
1 Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
VDDEXT
2.5 V or 3.3V Nominal
Min
Max
Unit
tSCLK + 1
ns
7.0
ns
0
ns
CLKOUT
CUD/CDG/CZM
tCIS
tCIH
tWCOUNT
Figure 33. Up/Down Counter/Rotary Encoder Timing
Rev. D | Page 63 of 88 | July 2013
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