ADSP-BF522BBCZ-3A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF522BBCZ-3A' PDF : 88 Pages View PDF
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
HOSTDP A/C Timing- Host Read Cycle
Table 56 describes the HOSTDP A/C Host Read Cycle timing
requirements.
Table 56. Host Read Cycle Timing Requirements
ADSP-BF522/ADSP-BF524/
ADSP-BF523/ADSP-BF525/
ADSP-BF526
ADSP-BF527
VDDEXT
1.8V Nominal
VDDEXT
2.5 V or 3.3V
Nominal
VDDEXT
1.8V Nominal
VDDEXT
2.5 V or 3.3V
Nominal
Parameter
Min
Max Min
Max Min
Max Min
Max
Unit
Timing Requirements
tSADRDL HOST_ADDR and HOST_CE Setup 4
4
4
4
ns
before HOST_RD falling edge
tHADRDH HOST_ADDR and HOST_CE Hold 2.5
2.5
2.5
2.5
ns
after HOST_RD rising edge
tRDWL HOST_RD pulse width low
tDRDYRDL +
tDRDYRDL +
tDRDYRDL +
tDRDYRDL +
ns
(ACK mode)
tRDYPRD +
tRDYPRD +
tRDYPRD +
tRDYPRD +
tDRDHRDY
tDRDHRDY
tDRDHRDY
tDRDHRDY
tRDWL HOST_RD pulse width low
1.5 × tSCLK
1.5 × tSCLK
1.5 × tSCLK
1.5 × tSCLK
ns
(INT mode)
+ 8.7
+ 8.7
+ 8.7
+ 8.7
tRDWH HOST_RD pulse width high or time 2 × tSCLK
2 × tSCLK
2 × tSCLK
2 × tSCLK
ns
between HOST_RD rising edge and
HOST_WR falling edge
tDRDHRDY HOST_RD rising edge delay after 2.0
2.0
0
0
ns
HOST_ACK rising edge (ACK mode)
Switching Characteristics
tSDATRDY Data valid prior HOST_ACK rising 4.5
3.5
4.5
3.5
ns
edge (ACK mode)
tDRDYRDL Host_ACK falling edge after
HOST_CE (ACK mode)
12.5
11.25
11.25
11.25 ns
tRDYPRD HOST_ACK low pulse-width for
NM1
NM1
NM1
NM1
ns
Read access (ACK mode)
tDDARWH Data disable after HOST_RD
tACC
Data valid after HOST_RD falling
edge (INT mode)
11.0
1.5 × tSCLK
9.0
1.5 × tSCLK
9.0
1.5 × tSCLK
9.0
ns
1.5 × tSCLK ns
tHDARWH Data hold after HOST_RD rising 1.0
1.0
1.0
1.0
ns
edge
1 NM (Not Measured) — This parameter is based on tSCLK. It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO
status and is system design dependent.
Rev. D | Page 64 of 88 | July 2013
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