ADSP-BF522BBCZ-3A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF522BBCZ-3A' PDF : 88 Pages View PDF
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
HOSTDP A/C Timing- Host Write Cycle
Table 57 describes the HOSTDP A/C Host Write Cycle timing
requirements.
Table 57. Host Write Cycle Timing Requirements
ADSP-BF522/ADSP-BF524/
ADSP-BF526
VDDEXT
1.8V Nominal
VDDEXT
2.5 V or 3.3V
Nominal
Parameter
Min
Max Min
Max
Timing Requirements
tSADWRL HOST_ADDR/HOST_CE Setup
4
4
before HOST_WR falling edge
tHADWRH HOST_ADDR/HOST_CE Hold
2.5
2.5
after HOST_WR rising edge
tWRWL
HOST_WR pulse width low
(ACK mode)
HOST_WR pulse width low
(INT mode)
tDRDYWRL +
tRDYPRD +
tDWRHRDY
1.5 × tSCLK
+ 8.7
tDRDYWRL +
tRDYPRD +
tDWRHRDY
1.5 × tSCLK
+ 8.7
tWRWH
HOST_WR pulse width high
or time between HOST_WR
rising edge and HOST_RD
falling edge
2 × tSCLK
2 × tSCLK
tDWRHRDY HOST_WR rising edge delay
2.0
2.0
after HOST_ACK rising edge
(ACK mode)
tHDATWH Data Hold after HOST_WR rising edge 2.5
2.5
tSDATWH Data Setup before HOST_WR
3.5
2.5
rising edge
Switching Characteristics
tDRDYWRL HOST_ACK falling edge after HOST_CE
12.5
11.5
asserted (ACK mode)
tRDYPWR HOST_ACK low pulse-width for Write
NM1
NM1
access (ACK mode)
ADSP-BF523/ADSP-BF525/
ADSP-BF527
VDDEXT
1.8V Nominal
VDDEXT
2.5 V or 3.3V
Nominal
Min
Max Min
Max
4
2.5
tDRDYWRL +
tRDYPRD +
tDWRHRDY
1.5 × tSCLK
+ 8.7
2 × tSCLK
4
2.5
tDRDYWRL +
tRDYPRD +
tDWRHRDY
1.5 × tSCLK
+ 8.7
2 × tSCLK
0
0
2.5
2.5
2.5
2.5
11.5
11.5
NM1
NM1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 NM (Not Measured) — This parameter is based on tSCLK. It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO
status and is system design dependent.
Rev. D | Page 66 of 88 | July 2013
Share Link: 
