ADSP-BF522BBCZ-3A View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF522BBCZ-3A' PDF : 88 Pages View PDF
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
10/100 Ethernet MAC Controller Timing
Table 58 through Table 63 and Figure 36 through Figure 41
describe the 10/100 Ethernet MAC Controller operations.
Table 58. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
VDDEXT
1.8V Nominal
VDDEXT
2.5 V or 3.3V Nominal
Parameter1
Min
Max
Min
Max
Unit
Timing Requirements
tERXCLKF
tERXCLKW
tERXCLKIS
tERXCLKIH
ERxCLK Frequency (fSCLK = SCLK Frequency)
ERxCLK Width (tERxCLK = ERxCLK Period)
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
None
25 + 1%
None
25 + 1%
MHz
tERxCLK × 40% tERxCLK × 60% tERxCLK × 35% tERxCLK × 65% ns
7.5
7.5
ns
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold) 7.5
7.5
ns
1 MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
ERx_CLK
tERXCLKW
tERXCLK
ERxD3–0
ERxDV
ERxER
tERXCLKIS tERXCLKIH
Figure 36. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Table 59. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Parameter1
VDDEXT
1.8V Nominal
Min
Max
VDDEXT
2.5 V or 3.3V Nominal
Min
Max
Unit
Switching Characteristics
tETXCLKF
tETXCLKW
tETXCLKOV
tETXCLKOH
ETxCLK Frequency (fSCLK = SCLK Frequency)
None
ETxCLK Width (tETxCLK = ETxCLK Period)
tETxCLK × 40%
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
25 + 1%
tETxCLK × 60%
20
None
tETxCLK × 35%
25 + 1%
tETxCLK × 65%
20
MHz
ns
ns
ETxCLK Rising Edge to Tx Output Invalid (Data Out 0
0
ns
Hold)
1 MII outputs synchronous to ETxCLK are ETxD3–0.
MIITxCLK
ETxD3–0
ETxEN
tETXCLKW
tETXCLKOH
tETXCLK
tETXCLKOV
Figure 37. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Rev. D | Page 68 of 88 | July 2013
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