ADSP-BF526KBCZ-4X View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF526KBCZ-4X' PDF : 80 Pages View PDF
Preliminary Technical Data
ADSP-BF522/523/524/525/526/527
Table 20. Electrical Characteristics For ADSP-BF523/525/527 Processors (Continued)
Parameter
Test Conditions
Min
Typical
Max
Unit
IDDHIBERNATE1, 2 Hibernate State Current
VDDEXT = VDDMEM =VDDRTC =
VDDUSB = 3.30 V,
VDDOTP = VPPOTP = 2.5 V,
TJ = 25°C, CLKIN = 0 MHz
with voltage regulator off
(VDDINT = 0 V)
40
μA
IDDRTC
VDDRTC Current
VDDRTC = 3.3 V, TJ = 25°C
20
μA
IDDUSB-FS
VDDUSB Current in Full/Low
Speed Mode
VDDUSB = 3.3 V, TJ = 25°C,
Full Speed USB Transmit
9
mA
IDDUSB-HS
VDDUSB Current in High Speed VDDUSB = 3.3 V, TJ = 25°C,
Mode
High Speed USB Transmit
25
mA
IDDSLEEP1, 3
VDDINIT Current in Sleep Mode fCCLK = 0 MHz, fSCLK > 0 MHz
IDDDEEPSLEEP1, 3 VDDINT Current in Deep Sleep fCCLK = 0 MHz, fSCLK = 0 MHz
Mode
Table 23 +
(0.43 × VDDINT ×
fSCLK)4
mA4
Table 23 mA
IDDINT3, 5
VDDINT Current
fCCLK > 0 MHz, fSCLK ≥ 0 MHz
Table 23 + mA
(Table 25 × ASF) +
(0.43 × VDDINT ×
fSCLK)
1 See the ADSP-BF522/523/524/525/526/527 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
2 Includes current on VDDEXT, VDDUSB, VDDMEM, VDDOTP, and VPPOTP supplies. Clock inputs are tied high or low.
3 Guaranteed maximum specifications.
4 Unit for VDDINT is V (Volts). Unit for fSCLK is MHz. Example: TBD V, TBD MHz would be TBD x TBD x TBD = TBD mA adder.
5 See Table 21 for the list of IDDINT power vectors covered.
Total Power Dissipation
Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. Electrical Characteristics on Page 31 shows the
current dissipation for internal circuitry (VDDINT). IDDDEEPSLEEP
specifies static power dissipation as a function of voltage
(VDDINT) and temperature (see Table 22 or Table 23), and IDDINT
specifies the total power specification for the listed test condi-
tions, including the dynamic component as a function of voltage
(VDDINT) and frequency (Table 24 or Table 25).
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF) which
represents application code running on the processor core and
L1/L2 memories (Table 21).
The ASF is combined with the CCLK Frequency and VDDINT
dependent data in Table 24 or Table 25 to calculate this part.
The second part is due to transistor switching in the system
clock (SCLK) domain, which is included in the IDDINT specifica-
tion equation.
Table 21. Activity Scaling Factors (ASF)1
IDDINT Power Vector
Activity Scaling Factor (ASF)
IDD-PEAK
1.29
IDD-HIGH
1.26
IDD-TYP
1.00
IDD-APP
0.88
IDD-NOP
0.72
IDD-IDLE
0.44
1 See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors
(EE-297). The power vector information also applies to the ADSP-BF52x
processors.
Rev. PrG | Page 33 of 80 | February 2009
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