Preliminary Technical Data
Asynchronous Memory Read Cycle Timing
Table 31. Asynchronous Memory Read Cycle Timing
Parameter
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
tHDAT
DATA15–0 Hold After CLKOUT
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDO
Output Delay After CLKOUT1
tHO
Output Hold After CLKOUT 1
1 Output balls include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
ADSP-BF522/523/524/525/526/527
VDDMEM = 1.8 V
Min
Max
2.1
0.9
4.0
0.2
6.0
0.8
VDDMEM = 2.5/3.3 V
Min
Max
Unit
2.1
ns
0.8
ns
4.0
ns
0.2
ns
6.0 ns
0.8
ns
CLKOUT
AMSx
SETUP
2 CYCLES
tDO
PROGRAMMED READ ACCESS
4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
tHO
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA15–0
ABE, ADDRESS
tDO
tSARDY
tHARDY
tHO
tHARDY
tSARDY
Figure 10. Asynchronous Memory Read Cycle Timing
tSDAT
READ
tHDAT
Rev. PrG | Page 39 of 80 | February 2009