ADSP-BF526KBCZ-4X View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF526KBCZ-4X' PDF : 80 Pages View PDF
ADSP-BF522/523/524/525/526/527
TIMING SPECIFICATIONS
Preliminary Technical Data
Clock and Reset Timing
Table 30 and Figure 9 describe clock and reset operations. Per
the CCLK and SCLK timing specifications in Table 12 to
Table 17, combinations of CLKIN and clock multipliers must
not select core/peripheral clocks in excess of the processor's
speed grade.
Table 30. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
CLKIN Period
tCKINL
CLKIN Low Pulse1
tCKINH
CLKIN High Pulse1
tWRST
RESET Asserted Pulse Width Low2
Switching Characteristic
20.0
10.0
10.0
11 × tCKIN
100.0
ns
ns
ns
ns
tBUFDLAY
CLKIN to CLKBUF Delay
10
ns
1 Applies to bypass mode and non-bypass mode.
2 Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
CLKIN
CLKBUF
tCKIN
tCKINL
tCKINH
tBUFDLAY
tBUFDLAY
RESET
tWRST
Figure 9. Clock and Reset Timing
Rev. PrG | Page 38 of 80 | February 2009
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