ADSP-BF526KBCZ-4X View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF526KBCZ-4X' PDF : 80 Pages View PDF
ADSP-BF522/523/524/525/526/527
Asynchronous Memory Write Cycle Timing
Table 32. Asynchronous Memory Write Cycle Timing
Parameter
Timing Requirements
tSARDY
ARDY Setup Before CLKOUT
tHARDY
ARDY Hold After CLKOUT
Switching Characteristics
tDDAT
tENDAT
tDO
tHO
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT1
Output Hold After CLKOUT 1
1 Output balls include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
Preliminary Technical Data
VDDMEM = 1.8 V
Min
Max
4.0
0.2
6.0
0.0
6.0
0.8
VDDMEM = 2.5/3.3 V
Min
Max
Unit
4.0
ns
0.2
ns
6.0 ns
0.0
ns
6.0 ns
0.8
ns
SETUP
2 CYCLES
ACCESS
PROGRAMMED WRITE EXTENDED HOLD
ACCESS 2 CYCLES
1 CYCLE 1 CYCLE
CLKOUT
t DO
tHO
AMSx
ABE1–0
ADDR19–1
AWE
ARDY
DATA15–0
ABE, ADDRESS
tDO
t SARDY
tHO
tHARDY
t ENDAT
WRITE DATA
tSARDY
tDDAT
Figure 11. Asynchronous Memory Write Cycle Timing
Rev. PrG | Page 40 of 80 | February 2009
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