ADSP-BF537BBCZ-5AV View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF537BBCZ-5AV' PDF : 68 Pages View PDF
ADSP-BF534/ADSP-BF536/ADSP-BF537
TIMING SPECIFICATIONS
Component specifications are subject to change
without notice.
Clock and Reset Timing
Table 22. Clock Input and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
tCKINL
tCKINH
tBUFDLAY
tWRST
tNOBOOT
CLKIN Period1, 2, 3, 4
CLKIN Low Pulse
CLKIN High Pulse
CLKIN to CLKBUF Delay
RESET Asserted Pulse Width Low
RESET Deassertion to First External Access Delay5
20.0
100.0
ns
8.0
ns
8.0
ns
10
ns
11 × tCKIN
ns
3 × tCKIN
5 × tCKIN
ns
1 Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in Table 10 through Table 14. Since
by default the PLL is multiplying the CLKIN frequency by 10 MHz, 300 MHz, and 400 MHz speed grade parts can not use the full CLKIN period range.
2 Applies to PLL bypass mode and PLL non bypass mode.
3 CLKIN frequency must not change on the fly.
4 If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
5 Applies when processor is configured in No Boot Mode (BMODE2-0 = b#000).
CLKIN
CLKBUF
tCKIN
tCKINL
tCKINH
RESET
tWRST
tBUFDLAY
tBUFDLAY
Figure 9. Clock and Reset Timing
Table 23. Power-Up Reset Timing
Parameter
Min
Timing Requirements
tRST_IN_PWR RESET Deasserted After the VDDINT, VDDEXT, VDDRTC, and CLKIN Pins Are Stable and 3500 × tCKIN
Within Specification
RESET
tRST_IN_PWR
Max
Unit
ns
CLKIN
VDD_SUPPLIES
In Figure 10, VDD_SUPPLIES is VDDINT, VDDEXT, VDDRTC
Figure 10. Power-Up Reset Timing
Rev. J | Page 30 of 68 | February 2014
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