ADSP-BF538F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF538F' PDF : 56 Pages View PDF
ADSP-BF538/ADSP-BF538F
Preliminary Technical Data
TIMING SPECIFICATIONS
Table 13 describes the timing requirements for the ADSP-
BF538/ADSP-BF538F processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock, system clock and Voltage Controlled Oscillator
(VCO) operating frequencies, as described in Absolute Maxi-
mum Ratings on Page 23. Table 14 describes Phase Locked
Loop operating conditions.
Table 13. Core and System Clock Requirements—ADSP-BF538/ADSP-BF538F—500 MHz
Parameter
fCCLK
Core Clock Frequency (VDDINT = 1.2 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 1.045 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.95 V minimum)
fCCLK
Core Clock Frequency (VDDINT = 0.85 V minimum)
Min
Max
500
444
400
333
Unit
MHz
MHz
MHz
MHz
Table 14. Phase Locked Loop Operating Conditions
Parameter
fVCO
Voltage Controlled Oscillator (VCO) Frequency
Min
Max
Unit
50
Max CCLK
MHz
Clock and Reset Timing
Table 15 and Figure 10 describe clock and reset operations. Per
Absolute Maximum Ratings on Page 23, combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 500/133 MHz.
Table 15. Clock and Reset Timing
Parameter
Min
Max
Unit
Timing Requirements
tCKIN
CLKIN Period
tCKINL
CLKIN Low Pulse1
tCKINH
CLKIN High Pulse1
tWRST
RESET Asserted Pulsewidth Low2
20.0
100.0
ns
8.0
ns
8.0
ns
11 tCKIN
ns
1 Applies to bypass mode and non-bypass mode.
2 Applies after power-up sequence is complete. At power-up, the processor’s internal phase locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).
CLKIN
RESET
tCKIN
tCKINL
tCKINH
tWRST
Figure 10. Clock and Reset Timing
Rev. PrD | Page 24 of 56 | May 2006
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