ADSP-BF538F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF538F' PDF : 56 Pages View PDF
ADSP-BF538/ADSP-BF538F
Table 17. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
tHDAT
DATA15–0 Hold After CLKOUT
tDANR
ARDY Negated Delay from AMSx Asserted1
tHAA
ARDY Asserted Hold After ARE Negated
tDO
Output Delay After CLKOUT2
tHO
Output Hold After CLKOUT2
1 S = number of programmed setup cycles, RA = number of programmed read access cycles.
2 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
Preliminary Technical Data
Min
Max
Unit
2.1
ns
0.8
ns
(S + RA – 2) × tSCLK
ns
0.0
ns
6.0
ns
0.8
ns
CLKOUT
AMSx
SETUP
2 CYCLES
tDO
PROGRAMMED READ ACCESS
4 CYCLES
ACCESS EXTENDED
HOLD
1 CYCLE
tH
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA15–0
BE, ADDRESS
tDO
tDANR
tH O
tHAA
Figure 12. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
tSDAT
READ
tHDAT
Rev. PrD | Page 26 of 56 | May 2006
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