ADSP-BF538F View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'ADSP-BF538F' PDF : 56 Pages View PDF
Preliminary Technical Data
Asynchronous Memory Write Cycle Timing
Table 18 and Table 19 on Page 28 and Figure 13 and Figure 14
on Page 28 describe asynchronous memory write cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 18. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Parameter
Timing Requirements
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
tDO
Output Delay After CLKOUT1
tHO
Output Hold After CLKOUT1
1 Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
1 CYCLE
HOLD
1 CYCLE
ADSP-BF538/ADSP-BF538F
Min
Max
Unit
TBD
ns
TBD
ns
6.0
ns
1.0
ns
6.0
ns
0.8
ns
CLKOUT
t DO
tHO
AMSx
ABE1–0
ADDR19–1
AWE
ARDY
DATA15–0
BE, ADDRESS
tDO
tHO
t SARDY
t ENDAT
t SARDY
WRITE DATA
tHARDY
t HARDY
t DDAT
Figure 13. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Rev. PrD | Page 27 of 56 | May 2006
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