AT90PWM81 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT90PWM81' PDF : 325 Pages View PDF
AT90PWM81/161
Figure 7-1. Reset logic.
DATA BUS
BODLEVEL [2..0]
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
Brown-out
Reset Circuit
Pull-up Resistor
Spike
Filter
RSTDIS
Watchdog
Oscillator
Clock
CK
Generator
CKSEL[3:0]
SUT[1:0]
Delay Counters
TIMEOUT
7.1.3
Table 7-1. Reset characteristics (1).
Symbol Parameter
Condition Minimum Typical Maximum Units
VPOT
Power-on reset threshold
voltage (rising)
Power-on reset threshold
voltage (falling) (2)
1.4
2.3
V
1.3
2.3
V
VRST
tRST
RESET pin threshold voltage
Minimum pulse width on
RESET pin
0.2VCC
0.85VCC
V
400
ns
Notes: 1. Values are guidelines only.
2. The power-on reset will not work unless the supply voltage has been below VPOT (falling).
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 7-1. The POR is activated whenever VCC is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
51
7734Q–AVR–02/12
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