Figure 7-2. MCU start-up, RESET tied to VCC.
VCC
VPOT
RESET
VRST
TIME-OUT
tTOUT
AT90PWM81/161
INTERNAL
RESET
Figure 7-3. MCU start-up, RESET extended externally.
VCC
RESET
VPOT
VRST
TIME-OUT
tTOUT
INTERNAL
RESET
7.1.4
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see Table 7-1 on page 51) will generate a reset, even if the clock is not
running. Shorter pulses are not guaranteed to generate a reset. When the applied signal
reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the
MCU after the Time-out period – tTOUT – has expired.
Figure 7-4. External reset during operation.
CC
52
7734Q–AVR–02/12