AT90PWM81 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
'AT90PWM81' PDF : 325 Pages View PDF
AT90PWM81/161
Figure 7-5. Brown-out reset during operation.
VCC
VBOT-
RESET
VBOT+
TIME-OUT
tTOUT
INTERNAL
RESET
7.1.6
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to
page 56 for details on operation of the Watchdog Timer.
Figure 7-6. Watchdog reset during operation.
CC
CK
7.2 System Control registers
7.2.1
MCUSR - MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
WDRF
BORF
EXTRF PORF
MCUSR
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
See Bit Description
• Bit 3 – WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
54
7734Q–AVR–02/12
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