ATA6617 View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATA6617
Atmel Corporation
'ATA6617' PDF : 308 Pages View PDF
In order to maximize performance and parallelism, the AVR® uses a Harvard architecture –
with separate memories and buses for program and data. Instructions in the Program memory
are executed with a single level pipelining. While one instruction is being executed, the next
instruction is pre-fetched from the Program memory. This concept enables instructions to be
executed in every clock cycle. The Program memory is In-System Reprogrammable Flash
memory.
The fast-access Register File contains 32 x 8-bit general purpose working registers with a sin-
gle clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation.
In a typical ALU operation, two operands are output from the Register File, the operation is
executed, and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant
and a register. Single register operations can also be executed in the ALU. After an arithmetic
operation, the Status Register is updated to reflect information about the result of the
operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word
format. Every Program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on
the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the
Stack size is only limited by the total SRAM size and the usage of the SRAM. All user pro-
grams must initialize the SP in the Reset routine (before subroutines or interrupts are
executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM
can easily be accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector
position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.
32 Atmel ATA6616/ATA6617
9132D–AUTO–12/10
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