ATA6617 View Datasheet(PDF) - Atmel Corporation
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MFG CO.
ATA6617
Atmel Corporation
'ATA6617' PDF : 308 Pages View PDF
Atmel ATA6616/ATA6617
4.4 AVR Memories
This section describes the different memories in the Atmel® ATtiny87/167. The AVR® architec-
ture has two main memory spaces, the Data memory and the Program memory space. In
addition, the Atmel ATtiny87/167 features an EEPROM Memory for data storage. All three
memory spaces are linear and regular.
4.4.1
Table 4-3. Memory Mapping.
Memory
Size
Flash
Start Address
End Address
32 Registers
I/O
Registers
Ext I/O
Registers
Internal
SRAM
EEPROM
Size
Start Address
End Address
Size
Start Address
End Address
Size
Start Address
End Address
Size
Start Address
End Address
Size
Start Address
End Address
Notes: 1. Byte address.
Mnemonic
Flash size
-
Flash end
-
-
-
-
-
-
-
-
-
ISRAM size
ISRAM start
ISRAM end
E2 size
-
E2 end
ATtiny87
ATtiny167
8Kbytes
16Kbytes
0x0000
0x1FFF(1)
0x0FFF(4.4.1)
0x3FFF(1)
0x1FFF(4.4.1)
32 bytes
0x0000
0x001F
64 bytes
0x0020
0x005F
160 bytes
0x0060
0x00FF
512 bytes
0x0100
0x02FF
512 bytes
0x0000
0x01FF
Word (16-bit) address.In-System Re-programmable Flash Program Memory
The Atmel ATtiny87/167 contains On-chip In-System Reprogrammable Flash memory for pro-
gram storage (see “Flash size” in Table 4-3 on page 39). Since all AVR instructions are 16 or
32 bits wide, the Flash is organized as 16 bits wide. Atmel ATtiny87/167 does not have sepa-
rate Boot Loader and Application Program sections, and the SPM instruction can be executed
from the entire Flash. See SELFPRGEN description in Section 4.21.2.1 “Store Program Mem-
ory Control and Status Register – SPMCSR” on page 244 for more details.
The Flash memory has an endurance of at least 10,000 write/erase cycles in automotive
range. The Atmel ATtiny87/167 Program Counter (PC) address the program memory loca-
tions. Section 4.22 “Memory Programming” on page 250 contains a detailed description on
Flash data serial downloading using the SPI pins.
Constant tables can be allocated within the entire Program memory address space (see the
LPM – Load Program memory instruction description).
Timing diagrams for instruction fetch and execution are presented in Section 4.3.6 “Instruction
Execution Timing” on page 36.
39
9132D–AUTO–12/10
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