ATA6617 View Datasheet(PDF) - Atmel Corporation

Part Name

Description

MFG CO.

ATA6617

8K/16K Flash Microcontroller with LIN Transceiver, 5V Regulator and Watchdog

Atmel Corporation 

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4.3.5.1

SPH and SPL – Stack Pointer Register

4.3.6

Bit

Read/Write

Initial Value

15

SP15

SP7

7

R/W

R/W

14

13

12

11

10

9

SP14

SP13

SP12

SP11

SP10

SP9

SP6

SP5

SP4

SP3

SP2

SP1

6

5

4

3

2

1

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

ISRAM end (See Table 4-3 on page 39)

8

SP8

SPH

SP0

SPL

0

R/W

R/W

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR®

CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for

the chip. No internal clock division is used.

Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the

Harvard architecture and the fast access Register File concept. This is the basic pipelining

concept to obtain up to 1MIPS per MHz with the corresponding unique results for functions per

cost, functions per clocks, and functions per power-unit.

Figure 4-5. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clkCPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an

ALU operation using two register operands is executed, and the result is stored back to the

destination register.

Figure 4-6. Single Cycle ALU Operation

T1

T2

T3

T4

clkCPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

36 Atmel ATA6616/ATA6617

9132D–AUTO–12/10

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