AU80610006225AASLBXC View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'AU80610006225AASLBXC' PDF : 80 Pages View PDF
Introduction
Term
Execute Disable Bit
Micro-FBGA
(G)MCH
GPU
ICH
IMC
Intel® 64 Technology
LCD
LLC
LVDS
MCP
NCTF
Processor
Processor Core
Rank
SCI
SMT
Description
The Execute Disable bit allows memory to be marked as executable or
non-executable, when combined with a supporting operating system.
If code attempts to run in non-executable memory the processor
raises an error to the operating system. This feature can prevent some
classes of viruses or worms that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. See the
Intel® 64 and IA-32 Architectures Software Developer's Manuals for
more detailed information.
Micro Flip Chip Ball Grid Array
Legacy component - Graphics Memory Controller Hub. Platforms
designed for the Intel Atom Processor D400 and D500 Series do not
use an (G)MCH.
Graphics Processing Unit
The legacy I/O Controller Hub component that contains the main PCI
interface, LPC interface, USB2, Serial ATA, and other I/O functions. It
communicates with the legacy (G)MCH over a proprietary interconnect
called DMI. Platforms designed for the Intel® Atom™ Processor D400
and D500 Series do not use an ICH.
Integrated Memory Controller
64-bit memory extensions to the IA-32 architecture.
Liquid Crystal Display
Last Level Cache. The LLC is the shared cache amongst all processor
execution cores
Low Voltage Differential Signaling
A high speed, low power data transmission standard used for display
connections to LCD panels.
Multi-Chip Package
Non-Critical to Function: NCTF locations are typically redundant
ground or non-critical reserved, so the loss of the solder joint
continuity at end of life conditions will not affect the overall product
functionality.
The 64-bit, single-core or multi-core component (package)
The term “processor core” refers to Si die itself which can contain
multiple execution cores. Each execution core has an instruction
cache, data cache, and 256-KB L2 cache. All execution cores share the
L3 cache.
A unit of DRAM corresponding four to eight devices in parallel, ignoring
ECC. These devices are usually, but not always, mounted on a single
side of a SO-DIMM.
System Control Interrupt. Used in ACPI protocol.
Simultaneous Multi-Threading
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Datasheet
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