AU80610006225AASLBXC View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'AU80610006225AASLBXC' PDF : 80 Pages View PDF
Signal Description
Table 2-6. Memory Reference and Compensation
Signal
Name
Description
Direction Type
DDR_RPD System Memory RCOMP signal. Refer Platform Design for
connection recommendation.
I/O
Analog
DDR_RPU System Memory RCOMP signal. Refer Platform Design for
connection recommendation.
I/O
Analog
DDR_VREF SDRAM Reference Voltage: external reference voltage
input for each DQ, DQS. Internal VREF is also supported.
I
Analog
DDR_PREF Reserved.
O
N/A
NOTE: Please refer to appropriate platform design guide for connections recommendations.
Table 2-7. Reset and Miscellaneous Signal
Signal Name
Description
Direction Type
RSTINB
Reset In: When asserted, this signal will asynchronously reset
the CPU logic. The signal is connected to the PCIRST# output
of the Intel NM10 Express Chipset.
This input should have a Schmitt trigger to avoid spurious
resets.
This signal is required to be 3.3-V tolerant.
PWROK
Power OK: When asserted, PWROK is an indication to the CPU
that core power has been stable for at least 10us.
This input should have a Schmitt trigger to avoid spurious
resets. This signal is required to be 3.3V tolerant.
DDR3_DRAM_PWROK
DDR3 power good monitor. Driven by platform logic for DDR3.
Reserved for DDR2 designs
DDR3_DRAMRST#
DDR3 DRAM reset. Reset signal from IMC to DRAM devices.
One for all SO-DIMMs. Used only in DDR3 mode. Reserved for
DDR2 designs.
RSVD_*
Reserved. Must be left unconnected on the board. Intel does
not recommend a test point on the board for this ball.
RSVD_NCTF_*
Reserved/non-critical to function. Pin for package mechanical
reliability. A test point may be placed on the board for this
ball.
RSVD_TP_*
Reserved-test-point. A test point may be placed on the board
for this ball.
XDP_RSVD_[17:0]
Reserved XDP debug signals.
NOTE: RSVD_* numbering needs to be observed for BSDL testing purposes.
I
HVCMOS
I
HVCMOS
I
CMOS-
1.5
O
SSTL-1.5
NC
I/O
I/O
20
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