AU80610006225AASLBXC View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'AU80610006225AASLBXC' PDF : 80 Pages View PDF
Signal Description
Table 2-4. CPU Legacy Signal
Signal Name
CPUPWRGOOD
SMI#
STPCLK#
Description
Direction
CPUPWRGOOD (Power Good) is a processor input.
The processor requires this signal to be a clean
indication that the clocks and power supplies are
stable and within their specifications. ‘Clean’ implies
that the signal will remain low (capable of sinking
leakage current), without glitches, from the time
that the power supplies are turned on until they
come within specification. The signal must then
transition monotonically to a high state. Rise time
and monotonicity requirements are shown in
I
Chapter 4 Electrical Specifications. CPUPWRGOOD
can be driven inactive at any time, but clocks and
power must again be stable before a subsequent
rising edge of CPUPWRGOOD. It must also meet the
minimum pulse width specification.
The CPUPWRGOOD signal must be supplied to the
processor; it is used to protect internal circuits
against voltage sequencing issues. It should be
driven high throughout boundary scan operation.
SMI# (System Management Interrupt) is asserted
asynchronously by system logic. On accepting a
System Management Interrupt, the processor saves
the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is
I
issued, and the processor begins program execution
from the SMM handler. If SMI#
is asserted during the deassertion of RESET# the
processor will tristate its outputs.
Stop clock.
I
GTLREF
GTL reference voltage for BPM* pins. Refer Platform
Design Guide for connection recommendation.
I
THERMDA_1
Thermal Diode - Anode & Cathode. Suffix 1 refers to
I
THERMDC_1
core #1. Suffix 1 refers to core #1.
O
THERMDA_2
THERMDC_2
Thermal Diode - Anode & Cathode. Suffix 2 refers to
core #2. Suffix 2 refers to core #2.
No connect for single-core processor.
I
O
BPM_1#[3:0]
Breakpoint and Performance Monitor Signals: Output
BPM_2#[3:0]
from the processor that indicate the status of
breakpoints and programmable counters used for
I/O
monitoring processor performance.
BPM_2# is no connect for single-core processor.
PRDY#
PRDY# is a processor output used by debug tools to
determine processor debug readiness.
I/O
Type
Core
CMOS
Core
CMOS
Core
CMOS
Core
Analog
Core
Analog
Core
Analog
GTL+
GTL+
18
Datasheet
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