AU80610006225AASLBXC View Datasheet(PDF) - Intel
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MFG CO.
'AU80610006225AASLBXC' PDF : 80 Pages View PDF
Signal Description
2 Signal Description
This chapter describes the processor signals. They are arranged in functional groups
according to their associated interface or category. The following notations are used to
describe the signal type:
Table 2-2. Signal Type
Notations
I
O
I/O
Signal Type
Input Pin
Output Pin
Bi-directional Input/Output Pin
The signal description also includes the type of buffer used for the particular signal.
Table 2-3. Signal Description Buffer Types
Signal
Description
CMOS
DMI
HVCMOS
DDR2
GTL+
TAP
Analog
Ref
Asynch
LVDS
SSTL - 1.8
CMOS buffers. 1.05 V tolerant
Direct Media Interface signals. These signals are compatible with PCI Express
1.0 Signalling Environment AC Specifications but are DC coupled. The buffers
are not 3.3V tolerant.
High Voltage buffers. 3.3V tolerant
DDR2 buffers: 1.8 V tolerant
Open Drain Gunning Transceiver Logic signaling technology. Refer to GTL+ I/O
Specification fro complete details.
Test Access Port signal
Analog reference or output. May be used as a threshold voltage or for buffer
compensation
Voltage reference signal
This signal is asynchronous and has no timing relationship with any reference
clock.
Low Voltage Differential Signalling. A high speed, low power data transmission
standard used for display connections to LCD panels.
Stub Series Termination Logic. These are 1.8V output capable buffers. 1.8V
tolerant.
Datasheet
15
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