AU80610006225AASLBXC View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'AU80610006225AASLBXC' PDF : 80 Pages View PDF
Signal Description
Table 2-4. CPU Legacy Signal
Signal Name
PREQ#
DPRSTP#
DPSLP#
Description
Direction
PREQ# is used by debug tools to request debug
operation of the processor.
I
DPRSTP# when asserted on the platform causes the
processor to transition from Deep Sleep State to the
Deeper Sleep State. To return to the Deep Sleep
State, DPRSTP# must be deasserted. DPRSTP# is
I
driven by the chipset. This function is not supported
for Intel Atom Processor D400 and D500 Series.
DPSLP# when asserted on the platform causes the
processor to transition from the Sleep State to the
Deep Sleep State. To return to the Sleep State,
DPSLP# must be de-asserted. DPSLP# is driven by
I
the chipset. This function is not supported for Intel
Atom Processor D400 and D500 Series.
Type
GTL+
Core
CMOS
Core
CMOS
2.2
System Memory Interface
Table 2-5. Memory Channel A
Signal Name
Description
DDR_A_CK_5:0
DDR_A_CKB_5:0
DDR_A_CSB_3:0
DDR_A_CKE_3:0
DDR_A_MA_14:0
DDR_A_BS_2:0
DDR_A_RASB
DDR_A_CASB
DDR_A_WEB
DDR_A_DQ_63:0
SDRAM Differential Clock: (3 per DIMM)
SDRAM Inverted Differential Clock: (3 per DIMM)
Chip Select: (1 per Rank)
Clock Enable: (power management - 1 per Rank)
Multiplexed Address
Bank Select
RAS Control Signal
CAS Control Signal
Write Enable Control Signal
Data Lines
Direction
O
O
O
O
O
O
O
O
O
I/O
DDR_A_DM_7:0
Data Mask: These signals are used to mask individual
bytes of data in the case of a partial write, and to interrupt
O
burst writes
DDR_A_DQS_7:0 Data Strobes
I/O
DDR_A_DQSB_7:0 Data Strobe Complements (DDR2)
I/O
DDR_A_ODT_3:0 On Die Termination: Active Termination Control (DDR2)
O
Type
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
SSTL-1.8
2x
SSTL-1.8
2x
SSTL-1.8
2x
SSTL-1.8
2x
SSTL-1.8
2x
Datasheet
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