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CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic

Part Name
Description
MFG CO.
CL-PD6833-QC-A
Cirrus-Logic
Cirrus Logic Cirrus-Logic
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Table 11-1. Extension Registers Quick Reference (cont.)
Register Name
I/O Index Memory Offset
Device Identification and Implementation Scheme
Mask Revision Byte
34h
Product ID Byte
35h
Device Capability Byte A
36h
Device Capability Byte B
37h
Device Implementation Byte A
38h
Device Implementation Byte B
39h
Device Implementation Byte C
3Ah
Device Implementation Byte D
3Bh
934h
935h
936h
937h
938h
939h
93Ah
93Bh
Extended
Index
Page
Number
159
159
160
161
162
163
164
165
166
11.1 Misc Control 1
Register Name: Misc Control 1
I/O Index: 16h
Memory Offset: 816h
Bit 7
Bit 6
Bit 5
Compatibility
Bit
Scratchpad Bits
R/W:0
R/W:00
Register Per: socket
Register Compatibility Type: ext.
Bit 4
Speaker
Enable
R/W:0
Bit 3
Bit 2
Pulse System
IRQ Interrupta
Pulse
Management
Interrupt a
R/W:0
R/W:0
Bit 1
VCC 3.3 V —
PME_CXT
R/W:0
Bit 0
Multimedia
Enable
R/W:0
a Bits 3:2 are valid only in External Hardware Interrupt Signalling mode.
Bit 0 — Multimedia Enable
0
Socket address lines are normal.
1
Socket address lines A[25:4] are high-impedance.
When this bit is set to ‘1’, the host tristates address lines A[25:4]. This bit has no effect unless the
Multimedia Arm bit is set to ‘1’ in Misc Control 3 (see Section 11.8.4 on page 151).
Bit 1 — VCC 3.3 V — PME_CXT
0
5 V activated when card power is to be applied.
1
3 V activated when card power is to be applied.
This bit determines whether 3 V or 5 V is applied to the socket when card power is applied; this bit
is used in conjunction with bit 4 of the Power Control register. This bit is part of the PME_CXT
(PME Context), a set of register bits that do not get reset or initialized if PME Enable is true when
the CL-PD6833 changes power states from D3 to D0 through a software PCI Bus Segment reset.
132
EXTENSION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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