CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
11.2 FIFO Control
Register Name: FIFO Control
I/O Index: 17h
Memory Offset: 817h
Bit 7
Bit 6
Bit 5
FIFO Status /
Flush FIFO
Disable
Memory
Posting
Disable
I/O
Posting
R/W:1
R/W:0
R/W:0
Register Per: socket
Register Compatibility Type: ext.
Bit 4
Reserved
R/W:0
Bit 3
CardBus-to-
PCI FIFO
Disable
R/W:0
Bit 2
Enable
CardBus-to-
CardBus
Posting
R/W:0
Bit 1
Bit 0
Memory Prefetch Disable
R/W:00
Bits 1:0 — Memory Prefetch Disable
This bit disables memory prefetch when the CardBus card is bus master and is performing
memory reads from host system memory.
Bit 1
Bit 0
Memory Prefetch
0
0
Prefetching is enabled.
1
1
Prefetching by CardBus master of PCI memory addresses is disabled.
NOTE: Bits 1:0 must be set to ‘00’ or to ‘11’; no other combinations are allowed.
Bit 2 — Enable CardBus-to-CardBus Posting
This bit controls CardBus-to-CardBus memory writes. It enables the posting of memory writes
when the CardBus card is bus master and is performing memory writes to the other CardBus card
in the CardBus controller. A safe policy is to set this bit only when there are cards operating in
32-bit CardBus mode in both sockets.
0
CardBus-to-CardBus posting is disabled. This bit must be disabled (cleared to ‘0’) if there is an R2
card in the socket being written.
1
CardBus-to-CardBus posting is enabled. This bit should be enabled only if there are CardBus cards in
both sockets.
Bit 3 — CardBus-to-PCI FIFO Disable
This bit disables the posting of memory writes to the PCI bus when the CardBus is bus master and
is performing memory writes to PCI host memory.
0
CardBus-to-PCI posting is enabled.
1
CardBus-to-PCI posting is disabled.
Bit 4 — Reserved
This bit must be written to ‘0’.
134
EXTENSION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
Share Link: 
