CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Bit 2 — Pulse Management Interrupt
0
Interrupts are passed to the IRQ[XX] pin as level-sensitive.
1
When an interrupt occurs, the IRQ[XX] pin is driven with the pulse train shown in Figure 11-1 and
allows for interrupt sharing.
This bit is valid only in External Hardware Interrupt Signalling mode. This bit selects Level or Pulse
mode operation of the IRQ[XX] pin. Note that a clock must be present on PCI_CLK for pulsed
interrupts to work. Refer to Section 15.3.2 for more information on interrupt timing.
IRQ[XX]
High-Z
DRIVEN HIGH
DRIVEN LOW
High-Z
High-Z = High-impedance
Figure 11-1. Pulse Mode Interrupts
Bit 3 — Pulse System IRQ Interrupt
0
Interrupts are passed to the IRQ[XX] pin as level-sensitive.
1
When an interrupt occurs, the IRQ[XX] pin is driven with the pulse train shown in Figure 11-1 and
allows for interrupt sharing.
This bit is valid only in External Hardware Interrupt Signalling mode. This bit selects Level or Pulse
mode operation of the IRQ[XX] pins.
Bit 4 — Speaker Enable
0
SPKR_OUT* is high-impedance.
1
SPKR_OUT* is driven from the XNOR of SPKR# from each enabled socket.
This bit determines whether the card SPKR# pin drives SPKR_OUT* (see page 21).
Bits 6:5 — Scratchpad Bits
Bit 7 — Compatibility Bit
June 1998
ADVANCE DATA BOOK v0.3
EXTENSION REGISTERS
133
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