CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Bit 5 — Disable I/O Posting
This bit disables posting of I/O writes when host PCI is bus master and is performing I/O writes to
CardBus or R2 cards.
0
Posting of I/O writes is enabled.
1
Posting of I/O writes is disabled.
When this bit is set, I/O writes from the PCI bus to a PC Card do not post to the FIFO, but are
issued directly to the PC Card.
Bit 6 — Disable Memory Posting
This bit disables posting of memory writes when host PCI is bus master and is performing memory
writes to CardBus or R2 cards.
0
Posting of memory writes is enabled.
1
Posting of memory writes is disabled.
When this bit is set, memory writes from the PCI bus to a PC Card do not post to the FIFO, but
are issued directly to the PC Card.
Bit 7 — FIFO Status / Flush FIFO
Value
0
1
I/O Read
FIFO not empty
FIFO empty
I/O Write
No operation occurs (default at reset)
Flush the FIFO
This bit controls FIFO operation and reports FIFO status. When this bit is set to ‘1’ during write
operations, all data in the FIFO is lost. During read operations, when this bit is ‘1’, the FIFO is
empty. During read operations when this bit is ‘0’, the FIFO has valid data.
This bit is used to ensure that the FIFO is empty before changing any registers; register writes are
retried if the FIFO is not empty.
FIFO contents are lost whenever any of the following occur:
q RST# pin (see page 19) is active.
q The card is removed.
q VCC Power bit (see page 95) is programmed to ‘0’.
q The Flush FIFO bit is set to ‘1’.
June 1998
ADVANCE DATA BOOK v0.3
EXTENSION REGISTERS
135
Share Link: 
