CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Table 2-3. Power Control and General Interface Pins (cont.)
Pin Name
SLATCH/
SMBCLK‡
SOUT#/ISLD/
IRQSER
SIN#/ISDAT/
GPIO2/LED2
Description
Pin Number Qty. I/O Pwr. Drive
Serial Latch / System Management Bus
Clock: This pin serves as output pin SLATCH
when used with the serial interface of Texas
Instruments’ TPS2206AIDF socket power
control chip, and serves as bidirectional pin
SMBCLK when used with Intel’s System
Management Bus used by Maxim’s socket
130
power control chip. This pin is open drain in the
SMBus mode of operation. In this mode an
external pull up is required.
This pin is used for configuration information
during hardware reset. Refer to Misc Control 3
register bit 2.
Serial Interrupt Output / Serial IRQ Load: In
PCI Interrupt Signalling mode, this pin is a no-
connect.
In PC/PCI Serial Interrupt Signalling mode, this
pin is the serial interrupt output, SOUT#.
In PCI/Way Interrupt Signalling mode, this pin is
205
the IRQSER signal, which is bidirectional.
In External-Hardware Interrupt Signalling mode,
this pin is the load signal, ISLD, used to load the
serially transmitted interrupt data into the exter-
nal serial-to-parallel shifters.
Serial Interrupt Input / Serial IRQ Data: In PCI
Interrupt Signalling mode, this pin is a no-
connect.
In PC/PCI Serial Interrupt Signalling mode, this
pin is the serial interrupt input, SIN# (see the
register at memory offset 930h, Misc Control 5
on page 158).
In External-Hardware Interrupt Signalling mode,
this pin is the IRQ vector data, ISDAT, that is
serially transmitted to the external serial-to-
parallel shifters.
206
General-Purpose Input/Output 2: This pin can
also be used for either input or output under the
control of the GPIO Input Control and GPIO
Output Control registers (see also the Pin
Multiplex Control 0 register at memory offset
914h). This pin is grouped with and powered
from the PCI_VCC pin.
LED2: This feature is only available in PCI/Way
interrupt signalling mode (see the register at
memory offset 930h, Misc Control 5 on page
158).
1
I/O-
PU
1
8 mA
(for
SLATCH)
1
I/O
4
PCI
Spec.
1
I/O
4
PCI
Spec.
June 1998
ADVANCE DATA BOOK v0.3
23
PIN INFORMATION
Share Link: 
