CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
3.1.2
CL-PD6833 R2 Windowing Capabilities
For full compatibility with existing software and to ensure compatibility with future R2 memory card and
R2 multifunction I/O cards, the CL-PD6833 provides seven programmable general-purpose windows per
socket. These windows default at reset to two I/O windows and five memory windows.
Any one of the seven windows can be programmed to respond on the PCI primary bus as either a memory
or I/O window and to issue either a memory or I/O cycle to the R2-compatible PC Card. For example, in
the case of a non-’X86 processor that must memory map I/O devices, a window would be set for memory
on the primary PCI side and I/O on the R2-compatible PC Card side. Tables 3-1 and 3-2 show the
programming options for each memory and I/O window.
Table 3-1. Memory Window Options
Memory
Window Option
Enable
Start Address
End Address
Offset Address
Upper Address
Data Size
Timing
Register Access
Setting
Write Protect
Description
Each of the seven windows can be programmed as a memory window and individually enabled.
DEVSEL# is not asserted for disabled windows.
This is the start address of the memory window within the selected 16-Mbyte page of PCI memory. The
start address can be programmed to reside on any 4-Kbyte boundary within the programmed page of
PCI memory.
This is the end address of the memory window within the selected 16-Mbyte page of PCI memory. The
end address can be programmed to reside on any 4-Kbyte boundary within the programmed page of
PCI memory. Only memory accesses between the start and end address get a response.
The offset address is added to the PCI address to determine the address for accessing the PC Card.
This allows the addresses in the PC Card address space to be different from the PCI address space.
The upper memory address specifies a 16-Mbyte page of PCI memory.
The size of accesses can be set manually to either 8 or 16 bits.
The timing of accesses (setup/command/recovery) can be set by either of two timing register sets:
Timer Set 0 or Timer Set 1.
The REG# pin can be enabled on a per-window basis so that any of the windows can be used for
accessing attribute memory.
If the window is programmed to be write-protected, then writes to the memory window are ignored
(reads are still performed normally).
26
INTRODUCTION TO THE CL-PD6833
ADVANCE DATA BOOK v0.3
June 1998
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