CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
PCI I/O Address Space
4 Gbytes*
PC Card Memory Address Space
64 Mbytes
Common Memory
Attribute
Memory
System I/O Map
End Address Registers
System I/O Map
Start Address Registers
.
.
.
.
I/O Window
Card Memory Window
Card Memory Map
Offset Address Registers
64 Kbytes
*NOTE: The CL-PD6833 only decodes the first 64 Kbytes of the PCI I/O space.
Figure 3-4. R2 I/O-to-Memory Window Organization
3.1.3
Zoomed Video Port
The CL-PD6833 supports the implementation of the ZV (zoomed video) Port at the PC Card interface.
The ZV Port provides a direct connection between a PC Card, a VGA controller, and an audio DAC. It
allows the PC Card to directly write video data to a graphics controller input port and audio data to a dig-
ital-to-analog converter.
The CL-PD6833 supports the ZV Port in the ‘bypass’ mode, during which the signals are directly routed
from the PC Card bus to the video port of the VGA controller. Rerouting is accomplished by tristating
address lines A[25:4] from the CL-PD6833. The CL-PD6833 enters the ZV Port mode when the
Multimedia Enable bit (bit 0 of the Misc Control 1 register at index 16h or memory offset 816h) is set to
a ‘1’. The CL-PD6833 has a Multimedia Arm bit (bit 7 of the Misc Control 3 register at I/O index 2Fh,
Extended Index 25h, or memory offset 925h), which works as an overriding control bit. Until the
Multimedia Arm bit is set, the Multimedia Enable bit does not tristate the address pins as previously
described.
Figure 3-5 shows an example of the ZV Port implementation using the CL-PD6833. For more details, refer
to the application note Zoomed Video Port Implementation (AN-PD10).
June 1998
ADVANCE DATA BOOK v0.3
29
INTRODUCTION TO THE CL-PD6833
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