CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Table 3-6. Card Detect and Voltage Sense
CD2#/CCD2# CD1#/CCD1#
GND
GND
GND
CVS2
CVS1
GND
CVS2
GND
CVS1
GND
GND
GND
GND
CVS1
GND
GND
GND
GND
CVS2
GND
CVS1
CVS2
VS2/CVS2
Open
GND
Open
CCD2#
GND
GND
CCD2#
CCD1#
Open
GND
CCD1#
VS1/CVS1
Open
GND
CCD1#
GND
CCD2#
Open
Open
Open
CCD2#
CCD1#
GND
Card Type
PC Card 16
PC Card 16
PC Card 32
PC Card 32
PC Card 32
PC Card 16
PC Card 32
PC Card 32
PC Card 32
Reserved
Reserved
Voltage (V)
5.0
3.3/x.x
3.3
3.3/x.x
3.3/x.x/y.y
x.x
x.x
x.x/y.y
y.y
Reserved
Reserved
3.2 Upgrading from the CL-PD6832 to the CL-PD6833
The CL-PD6833 is a direct pin replacement for the CL-PD6832. The CL-PD6833 has support for ACPI
and GPIO pins to control the external buffers for ZV (zoomed video) port. These features have to be con-
sidered when designing a board that can accept the CL-PD6832 or the CL-PD6833 in the same footprint.
Table 3-7 depicts the essence of upgrading. The register bits in Table 3-7 are part of the PME_CXT (PME
Context). They do not get reset or initialized if PME enable is true when the CL-PD6833 changes power
states from D3 to D0 through a software PCI bus segment reset.
Table 3-7. Upgrading from the CL-PD6832 to the CL-PD6833
Pin
Number
CL-PD6832–Only
Function
CL-PD6833 Function /
Bit Values
CL-PD6833 Function /
Bit Values
Register / Bits
128
SPKR_OUT*
133
LEDOUT*/HW_SUSPEND#
203
INTA#
204
INTB#/RI_OUT*
206
SIN#/ISDAT
PME#/10
LED1*
PME#/10
LED2*
GPIO3/01
GPIO4/01
GPIO1/01
GPIO2/01
914h / 5:4
914h / 7:6
914h / 1:0
915h / 1:0
914h / 3:2
The CL-PD6833 powers up in a default state with CL-PD6832 functionality. The only exception is pin 131.
For ACPI compliance, the board has to be designed so that during the period before POWERGOOD goes
true, pin 131 is held low while PCI_RST# is asserted low. During all other times, this pin behaves as
SDATA/SMBDATA output. The following example circuit can be used to provide the PCI_RST# signal to
pin 131 only when POWERGOOD is not true. When the POWERGOOD signal is not active, the FET
38
INTRODUCTION TO THE CL-PD6833
ADVANCE DATA BOOK v0.3
June 1998
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