CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
conducts and connects PCI_RST# to pin 131. During this time, the CL-PD6833 internally ensures that pin
131 is an input. Thereafter, when POWERGOOD is active, pins 131 and 207 are disconnected since the
FET is not conducting. Pin 131 can then become an output and drive either SDATA or SMBDATA.
PIN 131
POWERGOOD
CL-PD6833
PCI_RST#
PIN 207
Figure 3-13. Power-on Detection for Power Management
Table 3-7 shows that after power-up, if registers 914h and 915h are programmed correctly, the
CL-PD6833 provides the PME# signal for ACPI compliance and/or provides the GPIO signals for ZV port
buffers. As shown in Table 3-7, PME# is available either on pin 133 or pin 204. Any illegal values (values
other than the ones shown in Table 3-7) programmed in these registers provide default CL-PD6832 pin
functionality for the corresponding bits.
Additional features of the CL-PD6833 are:
q In PCI Configuration Space, register 98h (see Configuration Miscellaneous 1 on page 73)
— bit 2 enables the PCI interrupts (INTA#, INTB#, ...) in the PCI/Way data stream.
— bit 8, when set to ‘1’ locks registers 914h and 915h.
— bit 9, when set to ‘1’ disables the Read Prefetch.
— bit 10, when set to ‘1’ disables Auto PC Card Reset during power state D3. This is a power saving feature.
3.2.1
Added Registers
The following registers have been added to the PCI Configuration space.
NOTE: PME_CXT (PME Context) is a set of register bits that do not get reset or initialized if PME Enable is true
when the CL-PD6833 changes power states from D3 to D0 through a software PCI Bus Segment reset.
3.2.1.1 Pin Multiplex Control 0 Register — PME_CXT
Register Name: Pin Multiplex Control 0 Register
PCI Memory Address: 914h
Bit 7
LED_OUT*/
HW_SUSP*/
PME#/GPIO4
Sel 1
R/W:0
Bit 6
LED_OUT*/
HW_SUSP*/
PME#/GPIO4
Sel 0
R/W:0
Bit 5
SPKR_OUT*/
GPIO3/
Sel 1
R/W:0
Bit 4
SPKR_OUT*/
GPIO3/
Sel 0
R/W:0
Bit 3
SIN#/ISDAT/
LED2*/GPIO2
Sel 1
R/W:0
Bit 2
SIN#/ISDAT/
LED2*/GPIO2
Sel 0
R/W:0
Bit 1
INTA#/LED1*/
GPIO1
Sel 1
R/W:0
Bit 0
INTA#/LED1*/
GPIO1
Sel 0
R/W:0
June 1998
ADVANCE DATA BOOK v0.3
39
INTRODUCTION TO THE CL-PD6833
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