CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Bit 19 — VGA Enable
This bit is not implemented.
Bit 20 — Reserved
Bit 21 — Master Abort Mode
This bit controls the behavior of the bridge when a master abort termination occurs on either
interface while bridge is the master.
0
Do not report master aborts and return all ones (FFFFFFFFh) on reads and discard data on writes to
the secondary master.
1
Report master aborts by signalling target abort, if possible, or by asserting SERR# if enabled.
Bit 22 — CardBus Reset
This bit forces a reset on the CardBus interface whenever it is set. The CardBus interface is also
reset whenever the RST# of the primary interface is asserted. Note that when the CRST# pin on
the CardBus interface is asserted (low), this does not mean the primary interface gets reset too.
Forcing a reset on the CardBus interface causes its configuration registers to reset to their default
states.
0
The reset signal to the CardBus card is inactive (high).
1
The reset signal to the CardBus card is active (low).
Bit 23 — IREQ-INT Enable
This bit is used to control the routing of PC Card IREQ (or CIREQ for CardBus cards) interrupts
to ISA IRQ or PCI INT pin. This is used only when the CL-PD6833 is programmed for non-PCI
style interrupts.
When this bit is set to ‘1’, PC Card IREQ (CIREQ) interrupts are routed to the ISA IRQ line (IRQ3,
4, 5, 7, 11, 12, 14, or 15) as indicated by the Interrupt and General Control register (memory
offset 803h). When this bit is set to ‘0’, PC Card IREQ (CIREQ) interrupts are routed to the INT
pin indicated by the Interrupt Pin register (memory offset 3Dh): INTA# for Socket A and INTB# for
Socket B. If the CL-PD6833 is programmed for Ring Indicate, then INTB# is used for ring out and
INTA# is used for both Sockets A and B, that is, INTB# is not available for function interrupt routing.
0
PC Card interrupts are routed to the INTX# pin indicated by the Interrupt Pin register.
1
PC Card interrupts are routed to the ISA IRQ pin indicated by the Interrupt and General Control
register.
Bit 24 — Memory 0 Prefetch Enable
This bit is not implemented.
0
Read Prefetching for memory window 0 is disabled.
1
Read Prefetching for memory window 0 is enabled.
Bit 25 — Memory 1 Prefetch Enable
This bit is not implemented.
0
Read Prefetching for memory window 1 is disabled.
1
Read Prefetching for memory window 0 is enabled.
June 1998
ADVANCE DATA BOOK v0.3
63
PCI CONFIGURATION REGISTERS
Share Link: 
