CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.16
Power Management Control and Status
Register Name: Power Management Control and Status
Offset: 84h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Register Per: socket
Bit 25
Bit 24
Byte 3
Bit 23
Bit 22
Bit 21
Data
R:00000000
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Byte 2
Byte 1
BPCC_EN
R:0
Bit 15
PME Status
R/W:Sticky
Bit 7
B2_B3#
R:0
Bit 14
Bit 13
Data Scale
R:00
Bit 6
Bit 5
Bit 12
Bit 4
Reserved
R:000000
Bit 11
Bit 10
Data Select
R:0000
Bit 3
Bit 2
Bit 9
Bit 1
Bit 8
PME Enable
(PME_En)
R/W:Sticky
Bit 0
Byte 0
Reserved
R:000000
Bits 1:0 — Power State
These two bits define the ACPI-defined power state of the socket interface.
Power State
R/W:00
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Power State of Socket Interface
D0
D1
D2
D3
Bits 7:2 — Reserved
Bit 8 — PME Enable (PME_En)
This bit enables the wake-up function of the CL-PD6833. When this bit is set, wake-ups are
signalled on the PME pin. When this bit is reset, no wake-ups are issued.
Bits 12:9 — Data Select
These bits read back ‘0’s to indicate that data selection is not supported.
Bits 14:13 — Data Scale
These bits read back ‘0’s to indicate that data readback is not supported.
68
PCI CONFIGURATION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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