CL-PD6833
PCI-to-CardBus Host Adapter
Bit 26 — Write Posting Enable
This bit enables posting of write data to the socket. If this bit is not set, the bridge must drain any
data in its buffers before accepting data for the socket. Each data word must then be accepted by
the target before the bridge can accept the next one from the source master. The bridge must not
release the source master until the last word is accepted by the target. Operating with write posting
disabled inhibits system performance.
0
Write posting is disabled.
1
Write posting is enabled.
Bits 31:27 — Reserved
64
PCI CONFIGURATION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998