CL-PD6833-QC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-QC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Bit 15— PME Status
This bit indicates that an event has occurred that, if the PME Enable bit is set, would cause PME
to be signalled. Writing a ‘1’ to this bit clears it to ‘0’, and writing ‘0’ to this bit has no effect.
Bits 21:16 — Reserved
Bit 22 — B2_B3# (B2/B3 Support for D3hot)
This bit set to ‘0’ and is not meaningful because bit 23 (BPCC_EN) is set to ‘0’.
Bit 23 — BPCC_EN (Bus Power / Clock Control Enable)
This bit is set to ‘0’. A ‘0’ indicates that the bus power/clock control policies have been disabled.
NOTE: Bits 23:16 always read back ‘0’s to indicate that the data register is not supported.
Bits 31:24 — Data
June 1998
ADVANCE DATA BOOK v0.3
69
PCI CONFIGURATION REGISTERS
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