CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
9.2.6
Card Memory Map 0–4 Offset Address High
Register Name: Card Memory Map 0–4 Offset Address High
I/O Index: 15h, 1Dh, 25h, 2Dh, 35h
Memory Offset: 815h, 81Dh, 825h, 82Dh, 835h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Register Per: socket
Register Compatibility Type: 365
Bit 2
Bit 1
Bit 0
Write Protect REG Setting
Offset Address 25:20
R/W:0
R/W:0
R/W:000000
There are five separate Card Memory Map Offset Address High registers, each with identical fields.
These registers are located at the following indexes:
Index (Socket A)
15h
1Dh
25h
2Dh
35h
Register
Card Memory Map 0 Offset Address High
Card Memory Map 1 Offset Address High
Card Memory Map 2 Offset Address High
Card Memory Map 3 Offset Address High
Card Memory Map 4 Offset Address High
Bits 5:0 — Offset Address 25:20
This field contains the most-significant six bits of the Offset Address. See the description of the
Offset Address field associated with bits 7:0 of the Card Memory Map 0–4 Offset Address Low
register (on page 114).
Bit 6 — REG Setting
0
REG# is not active for accesses made through this window.
1
REG# is active for accesses made through this window.
This bit determines whether REG# is active for accesses made through this window. CIS (card
information structure) memory is accessed by setting this bit to ‘1’.
Bit 7 — Write Protect
0
Writes to the card through this window are allowed.
1
Writes to the card through this window are not allowed.
This bit determines whether writes to the card through this window are allowed.
June 1998
ADVANCE DATA BOOK v0.3
WINDOW MAPPING REGISTERS
115
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