CL-PD6833
PCI-to-CardBus Host Adapter
11.9.5 Device Implementation Byte A
Register Name: Device Implementation Byte A
I/O Index: 38h
Memory Offset: 938h
Bit 7
Bit 6
Bit 5
Bit 4
RI_OUT Wired
Hardware
Suspend
Wired
GPSTB B
Wired
GPSTB A
Wired
R/W:0
R/W:0
R/W:0
R/W:0
Bit 3
VS1/VS2
Wired
R/W:1
Register Per: chip
Register Compatibility Type: ext.
Bit 2
Slave DMA
Wired
R/W:0
Bit 1
Sockets
Present 1
R/W:0
Bit 0
Sockets
Present 0
R/W:1
All bits of this byte are read/write. Device reset defaults are specific to each device. A BIOS write to this
byte before bringing of socket services sets these bits to reflect which of these features are supported in
the system implementation.
Bit 0 — Sockets Present 0
Bit 1 — Sockets Present 1
Bits 1:0 indicate the socket features supported in the system implementation.
Bit 2 — Slave DMA Wired
This bit indicates whether the system is wired to allow the slave DMA feature to be used.
Bit 3 — VS1/VS2 Wired
When this bit is ‘1’, the system is wired to use the VS1/VS2 pin. When this bit is ‘0’ the system is
not wired and is not capable of using the VS1/VS2 pin.
Bits 5:4 — GPSTB [B:A] Wired
Bits 5:4 indicate the general-purpose strobe features supported in the system implementation.
Bit 6 — Hardware Suspend Wired
A ‘1’ indicates that a pin on the device designated as a hardware control of suspend for deep
power saving has been connected to system circuitry designed for power management.
Bit 7 — RI_OUT Wired
A ‘1’ indicates that a pin on the device designated as ‘RI_OUT’ has been connected to ring indicate
circuitry. Socket services must set the Misc. Control 2 register (I/O index 1E) bit 7 to a ‘1’, thereby
enabling this alternate pin definition as it has been wired.
A value of ‘1’ implies that the RI_OUT*/INTB# pin is not connected to the PCI bus INTB# line, but
is instead connected to an SMI type system function designed to wake up a system on modem
ring.
June 1998
ADVANCE DATA BOOK v0.3
EXTENSION REGISTERS
163