CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
12.2 Command Timing 0–1
Register Name: Command Timing 0–1
I/O Index: 3Bh, 3Eh
Memory Offset: 83Bh, 83Eh
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Command Multiplier Value
R:00
R/W:000111/010001
There are two separate Command Timing registers, each with identical fields. These registers are
located at the following indexes:
I/O Index
3Bh
3Eh
Memory Offset
83Bh
83Eh
Command Timing (Socket A)
Command Timing 0
Command Timing 1
The Command Timing register for each timer set controls how long a PC Card cycle’s command (that is,
OE#, WE#, IORD#, IOWR#; see Table 2-2 on page 15) active time is, in terms of the number of internal
clock cycles.
The overall command timing length C is programmed by selecting a multiplier value (bits 5:0) to produce
the overall command timing length according to the following formula:
C = Nval + 1
Equation 12-2
The value of C, representing the number of clock cycles for a command, is then multiplied by the clock
period to determine the actual command active time (see Section 15.3.3 for further discussion).
Bits 5:0 — Command Multiplier Value
This field indicates an integer value Nval from 0 to 63; it controls the length that a command is
active.
Bits 7:6 — Reserved
168
TIMING REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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