CL-PD6833
PCI-to-CardBus Host Adapter
11.9.8 Device Implementation Byte D
Register Name: Device Implementation Byte D
I/O Index: 3Bh
Memory Offset: 93Bh
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
RFU
Clk Option
Wired
RFU
R/W:0
R/W:0
R/W:0
Register Per: chip
Register Compatibility Type: ext.
Bit 26
Bit 25
LOCK# Wired
R/W:1
Bit 24
CLKRUN#
Wired
R/W:1
Bit 24 — CLKRUN# Wired
A value of ‘1’ indicates that the system supports CLKRUN# protocol. A value of ‘0’ indicates that
the system does not support CLKRUN# protocol.
Bit 25 — LOCK# Wired
A value of ‘1’ indicates that the system supports a LOCK#. A value of ‘0’ indicates that the system
does not support a LOCK#.
Bits 29:26 — RFU (reserved for future use)
Bit 30 — Clk Option Wired
A value of ‘1’ indicates that an external clock is available to the CL-PD6833. A value of ‘0’ indicates
that an external clock is not available to the CL-PD6833.
Bit 31 — RFU (reserved for future use)
166
EXTENSION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998