CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
12.3 Recovery Timing 0–1
Register Name: Recovery Timing 0–1
I/O Index: 3Ch, 3Fh
Memory Offset: 83Ch, 83Fh
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Recovery Multiplier Value
R:00
R/W:000100/000100
There are two separate Recovery Timing registers, each with identical fields. These registers are located
at the following indexes:
I/O Index
3Ch
3Fh
Memory Offset
83Ch
83Fh
Recovery Timing (Socket A)
Recovery Timing 0
Recovery Timing 1
The Recovery Timing register for each timer set controls how long a PC Card cycle’s command (that is,
OE#, WE#, IORD#, IOWR#; see Table 2-2 on page 15) recovery time is, in terms of the number of internal
clock cycles.
The overall command recovery timing length R is programmed by selecting a multiplier value (bits 5:0) to
produce the overall command recovery timing length according to the following formula:
R = Nval + 1
Equation 12-3
The value of R, representing the number of clock cycles for command recovery, is then multiplied by the
clock period to determine the actual command recovery time (see Section 15.3.3 for further discussion).
Bits 5:0 — Recovery Multiplier Value
This field indicates an integer value Nval from 0 to 63; it controls the length of recovery time after
a command is active.
Bits 7:6 — Reserved
June 1998
ADVANCE DATA BOOK v0.3
TIMING REGISTERS
169
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