CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
12. TIMING REGISTERS
Table 12-1. Timing Registers Quick Reference
Register Name
Setup Timing 0–1
Command Timing 0–1
Recovery Timing 0–1
I/O Index
3Ah, 3Dh
3Bh, 3Eh
3Ch, 3Fh
Memory Offset
83Ah, 83Dh
83Bh, 83Eh
83Ch, 83Fh
Page Number
167
168
169
The following information about the timing registers is important:
q All timing registers take effect immediately and should only be changed when the FIFO is empty (see the
FIFO Control register on page 134).
q Selection of Timer Set 0 or Timer Set 1 register sets is controlled by I/O Window Control bits 3 and 7.
12.1 Setup Timing 0–1
Register Name: Setup Timing 0–1
I/O Index: 3Ah, 3Dh
Memory Offset: 83Ah, 83Dh
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Setup Multiplier Value
R:00
R/W:000000/000011
There are two separate Setup Timing registers, each with identical fields. These registers are located at
the following indexes:
Index (Socket A)
Setup Timing
3Ah
Setup Timing 0
3Dh
Setup Timing 1
The Setup Timing register for each timer set controls how long a PC Card cycle’s command (that is, OE#,
WE#, IORD#, IOWR#; see Table 2-2 on page 15) setup time is, in terms of the number of internal clock
cycles.
The overall command setup timing length S is programmed by selecting a value (bits 5:0) to produce the
overall command setup timing length according to the following formula:
S = Nval + 1
Equation 12-1
The value of S, representing the number of clock cycles for command setup, is then multiplied by the clock
period to determine the actual command setup time (see Section 15.3.3 for further discussion).
Bits 5:0 — Setup Multiplier Value
This field indicates an integer value Nval from 0 to 63 to control the length of setup time before a
command becomes active.
Bits 7:6 — Reserved
June 1998
ADVANCE DATA BOOK v0.3
TIMING REGISTERS
167
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