CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.12 Interrupt Line, Interrupt Pin, and Bridge Control
Byte 3
Bridge
Control
(high)
Byte 2
Bridge
Control
(low)
Register Name: Interrupt Line, Interrupt Pin, and Bridge Control
Offset: 3Ch
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Register Per: socket
Bit 25
Bit 24
Bit 23
IREQ-INT
Enable
R/W:0
Bit 15
Bit 22
CardBus
Reset
R/W:1
Bit 14
Reserved
R:00000
Bit 21
Master Abort
Mode
R/W:0
Bit 13
Bit 20
Reserved
R:0
Bit 12
Bit 19
VGA Enable
R:0
Bit 11
Write Posting
Enable
R/W:0
Bit 18
ISA Enable
R:0
Bit 10
Memory 1
Prefetch
Enable
R:0
Bit 17
CardBus
System Error
(SERR#)
Enable
R/W:0
Bit 9
Memory 0
Prefetch
Enable
R:0
Bit 16
CardBus
Parity Error
Response
Enable
R/W:0
Bit 8
Byte 1
Interrupt Pin
Byte 0
Interrupt
Line
Bit 7
Bit 6
Bit 5
Interrupt Pin
R:00000001/00000010
Bit 4
Bit 3
Interrupt Line
R/W:00000000
Bit 2
Bit 1
Bit 0
Bits 7:0 — Interrupt Line
This register is used by software to communicate the routing of the interrupts (INTA# for Socket A
and INTB# for Socket B).
Bits 15:8 — Interrupt Pin
These read-only registers indicate that the CL-PD6833 requires one interrupt line per function
(Socket A and Socket B) and that these lines are INTA# and INTB#.
Bit 16 — CardBus Parity Error Response Enable
This bit determines the response to parity errors on the CardBus interface.
0
Ignore address/data parity errors on the CardBus interface.
1
Enable parity error reporting and detection on the CardBus interface.
Bit 17 — CardBus System Error (SERR#) Enable
This bit controls the forwarding of the CardBus interface SERR# assertions to the primary
interface.
0
Disable forwarding of CardBus interface SERR# to the primary interface.
1
Enable forwarding of CardBus interface SERR# to the primary interface.
Bit 18 — ISA Enable
This bit is not implemented.
62
PCI CONFIGURATION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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