CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.15 Power Management Registers
Register Name: Power Management Registers
Offset: 80h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Register Per: socket
Bit 25
Bit 24
Byte 3
PME# from
D3 cold
PME# from
D3 hot
PME# from PME# from D1 PME# from
D2
D0
D2 support
D1 support
Dynamic Data
support
Byte 2
R:1
Bit 23
R:1
Bit 22
Reserved
R:0
Bit 15
Bit 14
R:1
Bit 21
Device
Specific
Initialization
R:0
Bit 13
R:1
Bit 20
Aux Power
Source
R:1
Bit 12
R:1
Bit 19
PME Clock
R:0
Bit 11
R:1
Bit 18
R:1
Bit 17
R:0
Bit 16
PCI Power Management Revision
Bit 10
R:001
Bit 9
Bit 8
Byte 1
Bit 7
Bit 6
Bit 5
Next Item Pointer
R:00000000
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 0
Capabilities ID
R:00000001
Bits 7:0 — Capabilities ID
This register identifies the rest of the registers in this section as a power management structure.
Bits 15:8 — Next Item Pointer
This register indicates that this section is the last of the capabilities structures.
Bits 18:16 — PCI Power Management Revision
The value ‘001’ indicates that the CL-PD6833 complies with version 1.0 of the PCI Power
Management Interface Specification.
Bits 31:19 — Power Management Capabilities
These bits indicate the following:
PME# can be asserted in power management state D0, D1, D2, and D3sw.
This device supports power management state D1 and D2.
This device does not require a full speed clock to operate.
This bridge is capable of Dynamic Clock Control and supports the CLK_RUN# protocol.
This device does not require device specific software prior to use.
This device is compliant with version 1.0 of the PCI Power Management Interface Specification.
June 1998
ADVANCE DATA BOOK v0.3
67
PCI CONFIGURATION REGISTERS
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